This invention relates to asynchronous bus to bus interfaces, and more particularly to a method for sequencing the channels of a multichannel FIFO device used to convey data from one bus to another bus.
There are a number of approaches to implementing asynchronous bus to bus interfaces. For example, U.S. Pat. No. 4,935,894, issued Jun. 19, 1990 to Ternes et al., describes a bus to bus interface that connects two asynchronous buses. The bus to bus interface includes two separate bus interfaces, a first bus interface that couples a first bus to a processor on a second bus, and a second bus interface that couples the second bus to a processor on the first bus. Each bus interface includes a first in first out (FIFO) register, interrupt logic, and transmitter/receiver logic. Communication through the bus interfaces is governed by a particular protocol that includes a 16-bit wide control word. The control word can contain data, as well as the address of a destination device.
U.S. Pat. No. 5,050,066, issued Sep. 17, 1991 to Myers et al., discloses an apparatus for queuing requests and replies on a pipelined packet bus. The apparatus connects one or more system buses to one or more local buses. The apparatus includes a RAM buffer for storing packet information corresponding to each request to be sent over a system bus in bus time slots allotted to each request, three send slots and three receive slots for keeping track of the states of respective three send and three receive requests that are stored in the RAM, nine send queue counters for stepping through a series of states to track an outgoing request and to track a corresponding incoming reply, and six receive queue counters for stepping through a series of states to track an incoming request and to track a corresponding reply. Status information as to the state of the slots is generated by an output MUX connected to the send and receive queues, the status information being used to control the incrementing or decrementing of the send and receive queue counters in accordance with a predetermined system bus protocol.
U.S. Pat. No. 5,003,463, issued Mar. 26, 1991 to Coyle et al. discloses a bus interface that couples a system bus to an I/O bus. The bus interface includes read and write buffer storage for buffering data transferred between the system bus and the I/O bus. The I/O bus includes signal lines that indicate when the read and the write buffers are full, and processors on the I/O bus are capable of differentiating between read and write buffer full conditions.
While these devices have generally performed adequately, they lack the flexibility to be more efficient.